1. Field of the Invention
The present invention relates to a phase-locked loop circuit, and in particular, to a phase-locked loop circuit capable of adjusting the frequency range of a spread spectrum clock.
2. Description of the Prior Art
All electronic equipment inherently generate electromagnetic interference (EMI) of one sort or another. EMI can cause physical harm to humans, and can have a negative impact on the other components of the computer. For example, EMI can cause the other components to experience instantaneous high voltage. The clock generator on the motherboard of a computer is always the main source of EMI in the computer. As a result, in order to suppress the EMI, a phase-locked loop with a spread spectrum circuit is often used to suppress the EMI.
FIG. 1A is a primary block diagram showing a conventional phase-locked loop (PLL) circuit. The PLL circuit 100 includes a N-divider 102, a M-divider 104, a phase frequency detector 106, a charge pump 108, a loop filter 110, and a voltage-controlled oscillator 112.
The N-divider 102 receives the reference signal with frequency Fref, divides the frequency Fref by N, and outputs the signal Fref/N. The M-divider 104 receives the feedback signal Fvco with the frequency Fvco outputted from the voltage-controlled oscillator 112, divides the frequency Fvco by M, and outputs the signal Fvco/M. Fref/N is the external clock signal, while Fvco/M is the internal clock signal. The phase frequency detector 106 detects both the frequency difference and phase difference between the signals Fref/N and Fvco/M, and outputs control signals xe2x80x9cUPxe2x80x9d and xe2x80x9cDNxe2x80x9d (i.e., down). When the phase of Fvco/M lags behind that of the Fref/N, the phase frequency detector 106 will enable the control signal xe2x80x9cUPxe2x80x9d. Inversely, when the phase of signal Fref/N lags behind that of the signal Fvco/M, the phase frequency detector 106 will enable the control signal xe2x80x9cDNxe2x80x9d. The charge pump 108 and the loop filter 110 are used for transforming the control signals xe2x80x9cUPxe2x80x9d and xe2x80x9cDNxe2x80x9d outputted from the phase frequency detector 106 into the control voltage Vc. When the control signal xe2x80x9cUPxe2x80x9d of the phase frequency detector 106 is enabled, the charge pump 108 generates a current Ich that flows into the loop filter 110 so as to increase the voltage Vc. Inversely, when the control signal xe2x80x9cDNxe2x80x9d of the phase frequency detector 106 is enabled, current is drained from the charge pump 108, so that the voltage Vc outputted from the loop filter 110 will decrease. The voltage-controlled oscillator 112 generates the feedback signal Fvco which has a frequency Fvco that varies according to the output voltage Vc from the loop filter 110. When the gain of the voltage-controlled oscillator is greater than 0 and Vc increases, the frequency Fvco will increase. On the other hand, when the gain of the voltage-controlled oscillator is smaller than 0 and Vc increases, the frequency Fvco will decrease. This process continues until, ideally, Fref/N is equal to Fvco/M. In the following description, the gain of the voltage-controlled oscillator is supposed to be greater than 0. Therefore, when the phase-locked loop circuit is stable, the relationship between Fvco and Fref thereof is represented by the following equation:
Fvco/M=Fref/N 
which translates to:
Fvco=Fref*M/Nxe2x80x83xe2x80x83(1) 
From equation (1), it is noted that only the values of the divisors, M and N, need to be controlled in order to control the value of Fvco. In the above-mentioned application, however, when the PLL is stable, Fvco is a constant frequency. When the constant frequency is transmitted on the trace in the motherboard, interference sources of this frequency and its harmonic component will be radiated. Therefore, the EMI specification (i.e., that the density of fc and its harmonics be within a certain range) cannot be met. As shown in FIGS. 1B(i) and 1B(ii), the amplitude at the frequency Fc exceeds the EMI specification. The interference level can be decreased if the PLL structure can be modified to uniformly spread out the energy of the signal Fvco within a predetermined range.
FIG. 2A shows an ideal spread spectrum on time domain and frequency domain. In this graph, the frequency of the signal Fvco periodically rises and falls, with the frequency Fc as the center between the frequency ranges of f1 and f2. FIG. 2B shows the relationship between the amplitude and frequency at the signal Fvco of FIG. 2A, and the amplitude falls within the EMI specification. Usually, the oscillating frequency of the voltage-controlled oscillator may be expressed by the following equation:
Fvco=F0+Kvco(Vcxe2x88x92V0)xe2x80x83xe2x80x83(2) 
wherein Fvco is the oscillating frequency of the voltage-controlled oscillator, F0 is the free running frequency when Vc=V0, Kvco is the slope of the voltage-controlled oscillator, which unit is Hz/V, Vc is the control voltage inputted to the voltage-controlled oscillator, and Vo is the threshold voltage of the voltage-controlled oscillator. The frequency of the voltage-controlled oscillator can be controlled only when Vc is greater than Vo. Therefore, if the PLL can control the Vc to vary linearly and periodically, the frequency Fvco will vary linearly and periodically in correspondence with Vc to thereby achieve the effects of spectrum spreading.
To achieve the above effect, some conventional applications have added another loop to control the Vc in the PLL. In this case, the frequency Fvco can vary linearly and periodically to achieve the effect of spectrum spreading. This method, however, has some disadvantages: (1) the circuit of the PLL becomes more complicated, (2) the entire structure tends to be unstable, and (3) the range of the spread spectrum is not easily controlled.
U.S. Pat. No. 5,610,955 discloses another attempt at achieving spread spectrum, which uses a method for periodically changing the M/N value in order to achieve the purpose of spectrum spreading. However, the disadvantage of this method is that the spread spectrum is not uniform. In other words, when the frequency reaches the upper and lower bounds, the frequency is constant within a period of time. This effect is illustrated in FIGS. 3A and 3B, where the outputted clocks Fvco may jut at frequencies f1 and f2 (see FIG. 3B) and exceed the EMI specification.
In view of the above-mentioned problems, it is therefore an object of the present invention to provide a PLL circuit that is capable of adjusting the range of spread spectrum, eliminating the jutting phenomenon on the frequency spectrum, and spreading the energy over a wider range.
To accomplish the objectives of the present invention, there is provided a circuit that includes a first voltage-controlled oscillator (VCO) that generates a feedback clock. The circuit further includes a phase frequency detector, a charge pump and a loop filter that together receive a reference clock and the feedback clock, and in response thereto, generates a first voltage signal. The circuit further includes a timing generator that generates a control signal having varying periods, and a voltage modulator that receives the first voltage signal and the control signal, and in response thereto generates a second voltage signal and a third voltage signal. The second voltage signal is provided to the first VCO. The circuit also includes a second VCO that receives the third voltage signal and which outputs a spread spectrum clock.
Since the present invention utilizes an FM/AM timing generator to control the voltage modulator, the PLL of the present invention realizes several advantages:
(1) since only one loop is used, the PLL circuit is simple and easy to maintain stable;
(2) the frequency range of the spread spectrum clock can be quantified, and the frequency of the spread spectrum clock can be controlled in a programmable way;
(3) since the time of frequency variation can be quantified and is programmable, the energy can be spread over a much wider range; and
(4) since the frequency of the spread spectrum clock varies periodically, there will be no constant frequency, no surge will be generated, and the spread spectrum clock will be uniform.